apeNEXT: basic HW	Schifano S. Fabio - INFN

About HW design:

• we use a SPMD approch

About the Node:

• double precision

• one normal operation per cycle ==> 8 ops / cycle

• large register file: 256 x 128bit

• overlapping of calculs and remote communication

About the network:

• three dimensional mesh topology

• bandwidth of the order of 200 Mbytes/sec/direction

• first neighbour and "L" communication patterns

• short startup latency to allow efficient transfer of short package data