APE software: the basic ideas
Schifano S. Fabio - INFN
Considering the previous points:
SIMD/SPMD architecture ==> the use of a data parallel language: TAO, a fortran-like dialect
the absence of dynamic instruction scheduler ==> a static instruction scheduler: the
shaker
What's and how the shaker works
?
APE has a VLIW (Very Long Instruction Words) architecure to achieve horizontal parallelism
APE has a pipelined architecture to achieve vertical parallelism
each assembler instruction is a microprogram that involves many hardware modules and spends more than one machine cycle.
MTOR 100 :7 0x1000
CNORM 200 100 101 102
CNORM 201 103 104 105
CNORM 203 200 201 106
RTOM 200 :3 0x2000
A x B + C ==> 8 complex ops
