Abstract

The supercomputer Leonardo is one of the three pre-exascale supercomputers that will form the European high-performance computing network of EuroHPC Joint Undertaking. Leonardo is co-funded by the EuroHPC and the Italian Ministry of Universities and Research and it’s hosted in the new CINECA’s data centre at the Bologna Big Data Technopole. The Technopole is considered the Italian Data Valley Hub where is located over 80% of total computing capacity in Italy. It’s a complex innovation ecosystem in the Emilia-Romagna region where a broadly ecosystem based of research, businesses and high-tech expertise are focused to extract value from data, carry-out direct decision-making, highlight correlations and protect the environment, citizens and their assets. The Technopole also host the supercomputer of ECMWF and it has been recently announced that the United Nations University (UNU) will establish a research and training institute to catalyse global collaboration and innovation in the utilization of big data and artificial intelligence to manage human habitat change.

Bio

Dr. Cesarini is a Project Manager & HPC Technology Specialist at the HPC department of CINECA where his works is focused on the design of the next-generation HPC architectures to define the strategic roadmap of Italian and European supercomputers. He is Vice-chair for Research of ETP4HP and he is part of the scientific advisory board of EuroHPC JU (RIAG). He manages for CINECA several European founded projects (EPI-SGA1, EPI-SGA2, EUPEX, REGALE, etc.) and national projects of the Italian Recovery and Resilience Plan (PNRR). He graduated in Computer Engineering from the University of Bologna (Italy) in 2014, where he also earned his Ph.D. in Electronics, Telecommunications, and Information Technologies Engineering in 2019.

Présentation

Abstract

Adastra, the latest supercomputer bought by GENCI and operated at CINES, is based on the latest exascale technologies provided by HPE and AMD. This supercomputer was ranked # in Top500 and #3 in Green500 in November 22. It is now ranked #12 in Top500 but keeps its 3rd position in Green500. The same architecture was deployed at Frontier (#1 Top500) to break the exascale for the first time in the Top500. The #3 machine, bought by EuroHPC and operated in LUMI Finland is also based on the same architecture. This architecture will be presented, and a first return on experience will be provided. On top of that, perspectives on what will be the next step for exascale in such architecture will be discussed.

Bio

Gabriel Hautreux est responsable du département HPC au CINES et a géré le déploiement du cluster de pointe Adastra, #11 au TOP500 et #3 au GREEN500 en novembre 2022. Ses activités actuelles visent à permettre à la communauté des chercheurs d’exploiter les applications utilisant les technologies exascales, ainsi qu’à augmenter l’efficacité énergétique des applications et à réduire l’empreinte énergétique et carbone des centres HPC.Il est spécialiste des architectures exascales, des nouveaux paradigmes de développement et de l’efficacité énergétique pour les architectures HPC et AI.

Gabriel Hautreux is in charge of the HPC department at CINES and managed the deployement of the leading edge cluster Adastra, #11 at TOP500 and #3 at GREEN500 in November 22. His current activities aim to enable the research community to leverage application using exascale technologies, as well as increasing the energy efficiency of applications and reducing the global energy and carbon footprint of HPC center. He is a specialist in exascale architectures, new development paradigms and energy efficiency for HPC and AI architectures..

Abstract

The modern supercomputer will leverage the new workloads of AI, Digital Twins, Quantum Computing, to solve the grand scientific challenges of the 21st century.

Bio

Frédéric Parienté (he/him) is a director in the solutions architecture and engineering group at NVIDIA. He is working with European customers in the Higher-Education & Research and Supercomputing sectors notably, on the adoption of HPC and AI. He is also managing the NVIDIA AI Technology Center (NVAITC) in EMEA, whose mission is to enable and accelerate AI research, education and adoption across the network of NVAITC Joint Labs.

Abstract

While Frontier is the 1st machine to break the Exaflop barrier, it is also one of the most power energy efficient systems in the world, sustaining real scientific production today. This prowess will continue in the coming months and years: AMD is driven by advancing both HPC and AI capabilities, providing TCO advantages while supporting the scientific community to adopt massively accelerated resources. Thus, AMD Instinct has a well-defined path to support users’ needs beyond Exascale.

Bio

Samuel Antao has a vast experience in optimisation and performance tuning for HPC applications and systems with focus on accelerators. His work spans hardware design with FPGAs, programming model research, compiler development and application optimisation for GPUs. Samuel has participated in several cutting-edge projects around HPC in Europe and in US, including CORAL, having spearheaded the GPU support for OpenMP in Clang/LLVM and helping numerous scientists and software developers to adopt the latest HPC technology and making the most out it. Samuel Antao is a Senior Member of Technical Staff with AMD and AMD lead to the LUMI Center of Excellence.

Résumé

[EN] As Europe consumes nearly 30% of the world’s supercomputing resources, only 5% of supercomputers are supplied in Europe and exactly 0% of the microprocessors powering them are designed here. The European Processor Initiative (EPI) is the EU response to this strategic autonomy challenge. SiPearl is the private company which was created within the EPI. Located in France, Germany, and Spain, SiPearl designs the next energy-efficient microprocessor for HPC. And the subsequent generations of SiPearl microprocessors will power Europe’s data centers and cloud infrastructures.

[FR] Quand l’Europe utilise près de 30% des ressources de super-calcul dans le monde, seulement 5% des supercalculateurs sont produits en Europe et exactement 0% des microprocesseurs qui les alimentent y sont conçus. EPI (European Processor Initiative) est la réponse de l’UE à ce défi de l’autonomie stratégique. SiPearl est l’entreprise privée qui a été créée dans le cadre d’EPI. Implantée en France, en Allemagne, et en Espagne, SiPearl conçoit les prochains microprocesseurs à haute efficacité énergétique pour supercalculateurs. Et les générations suivantes de microprocesseurs de SiPearl alimenteront les centres de données et les infrastructures cloud de l’Europe.

Bio

[EN] Thierry Lelégard is head of platform security at SiPearl, in charge of product security architecture and cloud and data centers requirements. He worked 20 years in media content security and piracy fighting at Canal+, NagraVision, STMicroelectronics and Orange. Before that, he worked on resilient clusters, operating systems and compilers at DEC (Digital Equipment Corporation).

[FR] Thierry Lelégard a la charge de l’architecture sécurité des produits ainsi que des besoins pour les infrastructures cloud et centres de données. Il a travaillé 20 ans dans la sécurité des contenus media et le combat contre le piratage chez Canal+, NagraVision, STMicroelectronics et Orange. Auparavant, il a travaillé sur les clusters résilients, les systèmes d’exploitation et les compilateurs chez DEC (Digital Equipment Corporation).

Abstract

The new open and royalty-free RISC-V ISA is attracting interest across the whole computing continuum, from microcontrollers to supercomputers. High-performance RISC-V processors and accelerators have been announced, but RISC-V-based HPC systems will need a holistic co-design effort, spanning memory, storage hierarchy interconnects and full software stack. In this talk we cover results from the Monte Cimone project aiming to create HPC systems based on RISC-V SoCs.

Bio

Andrea Bartolini is an Associate Professor at the Department of Electrical, Electronic and Information Engineering (Guglielmo Marconi) at the University of Bologna. He was a postdoctoral researcher with the Integrated Systems Laboratory, Swiss Federal Institute of Technology, Zurich. He has authored or co-authored more than 135 papers in peer-reviewed international journals and conferences, and several book chapters with a focus on dynamic resource management—ranging from embedded to large-scale HPC systems. He has collaborated with several international researchers and companies. Andrea Bartolini has been the main responsible for the design of advanced power management and monitoring support on the first Cavium ThunderX cluster, the D.A.V.I.D.E. and Marconi100 supercomputers. Since 2018, Andrea Bartolini has served as the technical leader for the European-processor-initiative power management design. In 2021, Andrea Bartolini collaborated with CINECA and E4 engineering in the design of the Monte Cimone HPC cluster – the first RISC-V HPC cluster.

Abstract 

Graphcore holds a unique position in the European AI ecosystem of companies capable to bring to market dedicated hardware along with a full software stack. We will present our singular approach allowing to drive unprecedented performances leveraging massive independent parallel computing capacity collocated with huge on-chip memory. We will explore how to such a compute density is achieved thanks to our MIMD architecture on latest process nodes and a BSP low-precision processing, together bringing best-in-class AI compute efficiency for performance, cost and energy consumption.

Bio

Gautier Soubrane is leading business development at Graphcore in EMEA and APAC regions. He cumulates 20+ years of experience in the semiconductor, telecom, finance and medical devices industries. He holds an MBA from IMD and a Master’s degree in Electronics and Telecom from ESEO. Prior to joining Graphcore, Gautier worked at DDN managing the AI business division in Europe and back in early 2000’s, he proudly contributed to launch the very first smartphones and single-chip RF+DSP/ARM solutions with Texas Instruments.

By 2025, with the introduction of the Exascale Jules Verne machine, the race to Zettascale will intensify. Fundamental challenges such as scalability, complexity management, human resource considerations, sustainability, environmental impact, energy efficiency, and data management during operation will become even more pressing than they are today. Additionally, the concept of Zettascale as a singular, centralized system may be questioned due to ecological, technical, and operational considerations. Factors such as the proliferation of data sources for scientific applications, stringent energy consumption constraints, and the evolving HPC market’s inclination towards cloud technology will likely foster a vision of Zettascale as an interconnected system-of-systems.

This round-table will present this forum speakers’ visions.